We can do that one of two ways, either under the simulate menu for start simulation or we can right-click "Simulate." If your layout does not show all objects such as your data, your process and your waveform, you can click on "Layout reset" and it will reset your layout. Now, we can move to library and open work, and our add_4 entity has been compiled, and we can simulate this now. Click "Open," and "OK." Now we have add_4.vhd loaded in our design, we can click "Compile," select it and we see that the design has compiled and we have a checkmark for completed design. This is assuming that you've copied over the add_4 file into the examples directory underneath model CMPE examples. Let's simulate, once the tool opens, click "Jumpstart" and then create a project, and for the project name, let's call this add_4, and "OK" I already have a project of that name, that's okay, yes, and let's add an existing file, browse and let's add the add_4.vhd file from the examples directory. Start ModelSim now and follow the steps as we simulate this code together. Let's simulate, we will use the provided add for VHDL code in ModelSim. In this example, we will use a four bit adder, with two data input buses of four bits, a carry in bit, a sum four bit output and a carry out bit.
You'll learn how to evaluate the correctness of your design using waveform analysis, and you will learn how to control the simulator to examine the code and it's output.
In this video, you will learn how to test a code using an HDL simulator. Hello and welcome to FPGA design for embedded systems.
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